New PPU, comments.
This commit is contained in:
Andrea Orrù
parent
f745c83b1c
commit
3e3fcce6f4
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@ -1 +0,0 @@
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-std=c++11
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@ -5,8 +5,8 @@ namespace Cartridge {
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int banksMap[8]; // Map virtual memory to ROM.
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u8* rom;
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u8* vRam;
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u8* rom; // ROM data.
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u8* vRam; // VRAM/VROM data.
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/* PRG-ROM access */
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template <bool wr> u8 access(u16 addr, u8 v)
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@ -19,7 +19,7 @@ template u8 access<0>(u16, u8); template u8 access<1>(u16, u8);
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/* CHR-ROM/RAM access */
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template <bool wr> u8 chr_access(u16 addr, u8 v)
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{
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return vRam[addr];
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return vRam[addr]; // TODO: support CHR-RAM.
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}
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template u8 chr_access<0>(u16, u8); template u8 chr_access<1>(u16, u8);
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@ -35,7 +35,7 @@ void load(const char* fname)
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// Read PRG-ROM and CHR-ROM:
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rom = new u8[0x4000 * prgRom_16k];
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vRam = new u8[0x2000 * chrRom_8k];
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vRam = new u8[0x2000 * chrRom_8k]; // TODO: CHR-RAM.
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fread( rom, 0x4000, prgRom_16k, f);
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fread(vRam, 0x2000, chrRom_8k , f);
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@ -1,6 +1,7 @@
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#include <cstdio>
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#include <cstdlib>
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#include "cartridge.hpp"
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#include "ppu.hpp"
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#include "cpu.hpp"
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namespace CPU {
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@ -14,7 +15,7 @@ Flags P;
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/* Cycle emulation */
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#define T tick()
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inline void tick() { return; }
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inline void tick() { PPU::step(); PPU::step(); PPU::step(); }
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/* Flags updating */
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inline void upd_cv(u8 x, u8 y, s16 r) { P.c = (r>0xFF); P.v = ~(x^y) & (x^r) & 0x80; }
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@ -27,6 +28,7 @@ template <bool wr> inline u8 access(u16 addr, u8 v = 0)
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{
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T; u8* r;
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if (addr < 0x2000) { r = &RAM[addr % 0x800]; if (wr) *r = v; return *r; } // RAM.
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else if (addr < 0x4000) { return PPU::access<wr>(addr % 8, v); } // PPU.
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else if (addr < 0x8000) { return 0; }
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else { return Cartridge::access<wr>(addr, v); } // ROM.
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}
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12
src/cpu.hpp
12
src/cpu.hpp
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@ -11,14 +11,14 @@ union Flags
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{
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struct
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{
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bool c : 1;
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bool z : 1;
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bool i : 1;
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bool d : 1;
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bool c : 1; // Carry.
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bool z : 1; // Zero.
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bool i : 1; // Interrupt priority.
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bool d : 1; // Decimal (useless).
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bool b : 1;
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bool unused : 1;
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bool v : 1;
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bool n : 1;
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bool v : 1; // Overflow.
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bool n : 1; // Negative.
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};
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u8 reg;
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188
src/ppu.cpp
188
src/ppu.cpp
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@ -4,68 +4,81 @@
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namespace PPU {
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u8 ciRam[0x800];
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u8 palette[0x20];
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u8 oam[0x100];
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u8 ciRam[0x800]; // VRAM for nametables.
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u8 palette[0x20]; // VRAM for palettes.
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u8 oam[0x100]; // VRAM for sprites.
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Addr vAddr, tAddr;
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u8 fX;
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u8 oamAddr;
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Ctrl ctrl;
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Mask mask;
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Status status;
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Addr vAddr, tAddr; // Loopy V, T.
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u8 fX; // Fine X.
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u8 oamAddr; // OAM address.
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static u8 rd(u16 addr)
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Ctrl ctrl; // PPUCTRL ($2000) register.
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Mask mask; // PPUMASK ($2001) register.
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Status status; // PPUSTATUS ($2002) register.
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// Background latches:
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u8 nt, at, bgL, bgH;
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// Background shift registers:
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u8 atShift; u16 bgShiftL, bgShiftH;
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// Rendering counters:
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int scanline, cycle;
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bool frameOdd;
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/* Access PPU memory */
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template <bool wr> u8 mem_access(u16 addr, u8 v = 0)
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{
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if (addr < 0x2000) return Cartridge::chr_access<0>(addr);
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else if (addr < 0x2800) return ciRam[addr - 0x2000];
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else if (addr < 0x3000) return 0x00;
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else if (addr < 0x3F00) return ciRam[addr - 0x3000];
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else return palette[addr % 0x20];
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}
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u8* ref;
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static u8 wr(u16 addr, u8 v)
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{
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if (addr < 0x2000) return Cartridge::chr_access<1>(addr, v);
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else if (addr < 0x2800) return ciRam[addr - 0x2000] = v;
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if (addr < 0x2000) return Cartridge::chr_access<wr>(addr, v); // CHR-ROM/RAM.
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else if (addr < 0x2800) ref = &ciRam[addr - 0x2000]; // Nametables.
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else if (addr < 0x3000) return 0x00;
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else if (addr < 0x3F00) return ciRam[addr - 0x3000] = v;
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else return palette[addr % 0x20] = v;
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}
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else if (addr < 0x3F00) ref = &ciRam[addr - 0x3000]; // Nametables (mirror).
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else ref = &palette[addr % 0x20]; // Palettes.
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if (wr) return *ref = v;
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else return *ref;
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}
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inline u8 rd(u16 addr) { return mem_access<0>(addr); }
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inline u8 wr(u16 addr, u8 v) { return mem_access<1>(addr, v); }
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/* Access PPU through registers. */
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template <bool write> u8 access(u16 index, u8 v)
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{
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static u8 res, buffer;
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static bool latch;
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static u8 res; // Result of the operation.
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static u8 buffer; // VRAM read buffer.
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static bool latch; // Detect second reading.
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/* Write into register */
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if (write)
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{
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res = v;
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switch (index)
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{
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case 0: ctrl.r = v; tAddr.nt = ctrl.nt; break;
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case 1: mask.r = v; break;
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case 3: oamAddr = v; break;
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case 4: oam[oamAddr++] = v; break;
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case 5:
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if (!latch) { fX = v & 7; tAddr.cX = v >> 3; }
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else { tAddr.fY = v & 7; tAddr.cY = v & 0x1F; }
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case 0: ctrl.r = v; tAddr.nt = ctrl.nt; break; // PPUCTRL ($2000).
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case 1: mask.r = v; break; // PPUMASK ($2001).
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case 3: oamAddr = v; break; // OAMADDR ($2003).
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case 4: oam[oamAddr++] = v; break; // OAMDATA ($2004).
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case 5: // PPUSCROLL ($2005).
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if (!latch) { fX = v & 7; tAddr.cX = v >> 3; } // First write.
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else { tAddr.fY = v & 7; tAddr.cY = v & 0x1F; } // Second write.
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latch = !latch;
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case 6:
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if (!latch) { tAddr.h = v & 0x3F; }
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else { tAddr.l = v; vAddr.r = tAddr.r; }
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case 6: // PPUADDR ($2006).
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if (!latch) { tAddr.h = v & 0x3F; } // First write.
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else { tAddr.l = v; vAddr.r = tAddr.r; } // Second write.
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latch = !latch;
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case 7: wr(vAddr.addr, v); vAddr.addr += ctrl.incr; break;
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case 7: wr(vAddr.addr, v); vAddr.addr += ctrl.incr ? 32 : 1; // PPUDATA ($2007).
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}
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}
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/* Read from register */
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else
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switch (index)
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{
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// PPUSTATUS ($2002):
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case 2: res = (res & 0x1F) | status.r; status.vBlank = 0; latch = 0; break;
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case 4: res = oam[oamAddr]; break;
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case 7:
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case 4: res = oam[oamAddr]; break; // OAMDATA ($2004).
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case 7: // PPUDATA ($2007).
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if (vAddr.addr <= 0x3EFF)
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{
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res = buffer;
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@ -73,13 +86,104 @@ template <bool write> u8 access(u16 index, u8 v)
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}
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else
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res = buffer = rd(vAddr.addr);
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vAddr.addr += ctrl.incr;
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break;
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vAddr.addr += ctrl.incr ? 32 : 1;
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}
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return res;
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}
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template u8 access<0>(u16, u8); template u8 access<1>(u16, u8);
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/* Calculate graphics addresses */
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inline u16 nt_addr() { return 0x2000 | (vAddr.addr); }
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inline u16 at_addr() { return 0x23C0 | (vAddr.nt << 10) | ((vAddr.cY / 4) << 3) | (vAddr.cX / 4); }
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inline u16 bg_addr() { return (ctrl.bgTbl * 0x1000) + (nt * 16) + vAddr.fY; }
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/* Increment the scroll by one pixel */
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inline void h_scroll() { if (vAddr.cX == 31) vAddr.r ^= 0x41F; else vAddr.cX++; }
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inline void v_scroll()
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{
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if (vAddr.fY < 7) vAddr.fY++;
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else
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{
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vAddr.fY = 0;
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if (vAddr.cY == 31) vAddr.cY = 0;
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else if (vAddr.cY == 29) { vAddr.cY = 0; vAddr.nt ^= 0b10; }
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else vAddr.cY++;
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}
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}
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/* Copy scrolling data from loopy T to loopy V */
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inline void h_update() { vAddr.r = (vAddr.r & ~0x041F) | (tAddr.r & 0x041F); }
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inline void v_update() { vAddr.r = (vAddr.r & ~0x7BE0) | (tAddr.r & 0x7BE0); }
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// Put new data into the shift registers:
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inline void reload_shift()
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{
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bgShiftL = (bgShiftL & 0xFF00) | bgL;
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bgShiftH = (bgShiftH & 0xFF00) | bgH;
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atShift = (atShift << 2) | (at & 0b11);
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}
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void pixel()
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{
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u8 px = ((atShift << 2) & 3) | ((bgShiftH << 1) & 1) | (bgShiftL & 1);
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bgShiftL <<= 1;
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bgShiftH <<= 1;
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}
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/* Execute a cycle of a scanline (prerender or visible) */
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template <bool pre> void scanline_()
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{
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static u16 addr;
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switch (cycle)
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{
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// Nametable fetching:
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TILE_PHASE_1: if (pre) status.vBlank = false; // Disable VBlank in prerender.
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addr = nt_addr(); break;
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TILE_PHASE_2: nt = rd(addr); break;
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// Attribute fetching:
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TILE_PHASE_3: addr = at_addr(); break;
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TILE_PHASE_4: at = rd(addr); if (vAddr.cY & 2) at >>= 4;
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if (vAddr.cX & 2) at >>= 2; break;
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// Background fetching (low bits):
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TILE_PHASE_5: addr = bg_addr(); break;
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TILE_PHASE_6: bgL = rd(addr); break;
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// Attribute fetching (high bits):
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TILE_PHASE_7: addr += 8; break;
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TILE_PHASE_8: bgH = rd(addr); h_scroll(); reload_shift(); break;
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case 256: bgH = rd(addr); v_scroll(); reload_shift(); break; // End of line.
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case 257: h_update(); // Update horizontal scrolling info.
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case 280 ... 304: // Vertical scrolling update in prerender scanline.
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if (pre) v_update();
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}
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}
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inline void scanline_visible() { scanline_<0>(); if (cycle >= 1 && cycle <= 256) pixel(); }
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inline void scanline_prerender() { scanline_<1>(); }
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/* Execute a PPU cycle. */
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void step()
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{
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switch (scanline)
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{
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case 0 ... 238: scanline_visible(); break; // Visible scanline.
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case 239: scanline_visible(); /*SDL_Flip(s);*/ break; // Last visible scanline.
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case 241: if (cycle == 1) status.vBlank = true; break; // Signal VBlank.
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case 261: // Pre-render scanline.
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scanline_prerender();
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if (cycle == 340)
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{
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// Restart from the first pixel on the screen:
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cycle = frameOdd ? 1 : 0; // Skip one cicle on odd frames.
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scanline = 0; frameOdd ^= 1;
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return; // Don't update scanline and cycle.
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}
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}
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// Update current cycle and scanline:
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cycle = (cycle + 1) % 341;
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scanline = cycle ? scanline : (scanline + 1);
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}
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}
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75
src/ppu.hpp
75
src/ppu.hpp
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@ -1,69 +1,78 @@
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#include "types.hpp"
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#ifndef PPU_HPP
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#define PPU_HPP
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namespace PPU {
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union Status
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{
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struct
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{
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unsigned bus : 5;
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unsigned sprOvf : 1;
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unsigned sprHit : 1;
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unsigned vBlank : 1;
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};
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u8 r;
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};
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/* PPUCTRL ($2000) register */
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union Ctrl
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{
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struct
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{
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unsigned nt : 2;
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unsigned incr : 1;
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unsigned sprTbl : 1;
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unsigned bgTbl : 1;
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unsigned sprSz : 1;
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unsigned slave : 1;
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unsigned nmi : 1;
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unsigned nt : 2; // Nametable ($2000 / $2400 / $2800 / $2C00).
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unsigned incr : 1; // Address increment (1 / 32).
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unsigned sprTbl : 1; // Sprite pattern table ($0000 / $1000).
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unsigned bgTbl : 1; // BG pattern table ($0000 / $1000).
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unsigned sprSz : 1; // Sprite size (8x8 / 16x8).
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unsigned slave : 1; // PPU master/slave.
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unsigned nmi : 1; // Enable NMI.
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};
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u8 r;
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};
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/* PPUMASK ($2001) register */
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union Mask
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{
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struct
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{
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unsigned gray : 1;
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unsigned bgLeft : 1;
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unsigned sprLeft : 1;
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unsigned bg : 1;
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unsigned spr : 1;
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unsigned red : 1;
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unsigned green : 1;
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unsigned blue : 1;
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unsigned gray : 1; // Grayscale.
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unsigned bgLeft : 1; // Show background in leftmost 8 pixels.
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unsigned sprLeft : 1; // Show sprite in leftmost 8 pixels.
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unsigned bg : 1; // Show background.
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unsigned spr : 1; // Show sprites.
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unsigned red : 1; // Intensify reds.
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unsigned green : 1; // Intensify greens.
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unsigned blue : 1; // Intensify blues.
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};
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u8 r;
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};
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/* PPUSTATUS ($2002) register */
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union Status
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{
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struct
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{
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unsigned bus : 5; // Not significant.
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unsigned sprOvf : 1; // Sprite overflow.
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unsigned sprHit : 1; // Sprite 0 Hit.
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unsigned vBlank : 1; // In VBlank?
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};
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u8 r;
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};
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/* Loopy's VRAM address */
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union Addr
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{
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struct
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{
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unsigned cX : 5;
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unsigned cY : 5;
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unsigned nt : 2;
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unsigned fY : 3;
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unsigned cX : 5; // Coarse X.
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unsigned cY : 5; // Coarse Y.
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unsigned nt : 2; // Nametable.
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unsigned fY : 3; // Fine Y.
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};
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struct
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{
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unsigned l : 8;
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unsigned h : 8;
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unsigned h : 7;
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};
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unsigned addr : 12;
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unsigned addr : 12; // Address part.
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unsigned r : 15;
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};
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void step();
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template <bool write> u8 access(u16 index, u8 v = 0);
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}
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#endif // PPU_HPP
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54
src/ppu_case.hpp
Normal file
54
src/ppu_case.hpp
Normal file
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@ -0,0 +1,54 @@
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#ifndef PPUCASE_HPP
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#define PPUCASE_HPP
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#define TILE_PHASE_1 \
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case 1: case 9: case 17: case 25: case 33: case 41: case 49: case 57: case 65: \
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case 73: case 81: case 89: case 97: case 105: case 113: case 121: case 129: case 137: \
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case 145: case 153: case 161: case 169: case 177: case 185: case 193: case 201: case 209: \
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case 217: case 225: case 233: case 241: case 249: case 321: case 329: case 337: case 339
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#define TILE_PHASE_2 \
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case 2: case 10: case 18: case 26: case 34: case 42: case 50: case 58: case 66: \
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case 74: case 82: case 90: case 98: case 106: case 114: case 122: case 130: case 138: \
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case 146: case 154: case 162: case 170: case 178: case 186: case 194: case 202: case 210: \
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case 218: case 226: case 234: case 242: case 250: case 322: case 330: case 338: case 340
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#define TILE_PHASE_3 \
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case 3: case 11: case 19: case 27: case 35: case 43: case 51: case 59: case 67: \
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case 75: case 83: case 91: case 99: case 107: case 115: case 123: case 131: case 139: \
|
||||
case 147: case 155: case 163: case 171: case 179: case 187: case 195: case 203: case 211: \
|
||||
case 219: case 227: case 235: case 243: case 251: case 323: case 331
|
||||
|
||||
#define TILE_PHASE_4 \
|
||||
case 4: case 12: case 20: case 28: case 36: case 44: case 52: case 60: case 68: \
|
||||
case 76: case 84: case 92: case 100: case 108: case 116: case 124: case 132: case 140: \
|
||||
case 148: case 156: case 164: case 172: case 180: case 188: case 196: case 204: case 212: \
|
||||
case 220: case 228: case 236: case 244: case 252: case 324: case 332
|
||||
|
||||
#define TILE_PHASE_5 \
|
||||
case 5: case 13: case 21: case 29: case 37: case 45: case 53: case 61: case 69: \
|
||||
case 77: case 85: case 93: case 101: case 109: case 117: case 125: case 133: case 141: \
|
||||
case 149: case 157: case 165: case 173: case 181: case 189: case 197: case 205: case 213: \
|
||||
case 221: case 229: case 237: case 245: case 253: case 325: case 333
|
||||
|
||||
#define TILE_PHASE_6 \
|
||||
case 6: case 14: case 22: case 30: case 38: case 46: case 54: case 62: case 70: \
|
||||
case 78: case 86: case 94: case 102: case 110: case 118: case 126: case 134: case 142: \
|
||||
case 150: case 158: case 166: case 174: case 182: case 190: case 198: case 206: case 214: \
|
||||
case 222: case 230: case 238: case 246: case 254: case 326: case 334
|
||||
|
||||
#define TILE_PHASE_7 \
|
||||
case 7: case 15: case 23: case 31: case 39: case 47: case 55: case 63: case 71: \
|
||||
case 79: case 87: case 95: case 103: case 111: case 119: case 127: case 135: case 143: \
|
||||
case 151: case 159: case 167: case 175: case 183: case 191: case 199: case 207: case 215: \
|
||||
case 223: case 231: case 239: case 247: case 255: case 327: case 335
|
||||
|
||||
#define TILE_PHASE_8 \
|
||||
case 8: case 16: case 24: case 32: case 40: case 48: case 56: case 64: case 72: \
|
||||
case 80: case 88: case 96: case 104: case 112: case 120: case 128: case 136: case 144: \
|
||||
case 152: case 160: case 168: case 176: case 184: case 192: case 200: case 208: case 216: \
|
||||
case 224: case 232: case 240: case 248: case 328: case 336
|
||||
|
||||
|
||||
#endif // PPUCASE_HPP
|
||||
Reference in a new issue