Refactoring + Updated SVI2 Addresses for Model 30
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9deb4f6f53
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93
zenpower.c
93
zenpower.c
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@ -59,8 +59,12 @@ MODULE_VERSION("0.1.8");
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#define F17H_M01H_REPORTED_TEMP_CTRL 0x00059800
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#define F17H_M01H_SVI 0x0005A000
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#define F17H_M01H_SVI_TEL_PLANE0 F17H_M01H_SVI + 0xc
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#define F17H_M01H_SVI_TEL_PLANE1 F17H_M01H_SVI + 0x10
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#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xC)
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#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
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#define F17H_M30H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0x14)
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#define F17H_M30H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
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#define F17H_M70H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0x10)
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#define F17H_M70H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0xC)
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#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
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#define F17H_TEMP_ADJUST_MASK 0x80000
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@ -203,10 +207,11 @@ static unsigned int get_ccd_temp(struct zenpower_data *data, u32 ccd_addr)
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}
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int static debug_addrs_arr[] = {
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F17H_M01H_SVI + 0x8, F17H_M01H_SVI_TEL_PLANE0, F17H_M01H_SVI_TEL_PLANE1,
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0x000598BC, 0x0005994C, F17H_M70H_CCD_TEMP(0), F17H_M70H_CCD_TEMP(1),
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F17H_M70H_CCD_TEMP(2), F17H_M70H_CCD_TEMP(3), F17H_M70H_CCD_TEMP(4),
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F17H_M70H_CCD_TEMP(5), F17H_M70H_CCD_TEMP(6), F17H_M70H_CCD_TEMP(7)
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F17H_M01H_SVI + 0x8, F17H_M01H_SVI + 0xC, F17H_M01H_SVI + 0x10,
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F17H_M01H_SVI + 0x14, 0x000598BC, 0x0005994C, F17H_M70H_CCD_TEMP(0),
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F17H_M70H_CCD_TEMP(1), F17H_M70H_CCD_TEMP(2), F17H_M70H_CCD_TEMP(3),
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F17H_M70H_CCD_TEMP(4), F17H_M70H_CCD_TEMP(5), F17H_M70H_CCD_TEMP(6),
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F17H_M70H_CCD_TEMP(7)
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};
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static ssize_t debug_data_show(struct device *dev,
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@ -446,10 +451,8 @@ static int zenpower_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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struct device *dev = &pdev->dev;
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struct zenpower_data *data;
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struct device *hwmon_dev;
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bool swapped_addr = false;
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bool sp3_chip = false; // SP3 cpus = threadripper / epyc
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u32 val, primary_plane, secondary_plane;
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int i, ccd_check = 0;
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u32 val;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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@ -484,26 +487,53 @@ static int zenpower_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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switch (boot_cpu_data.x86_model) {
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case 0x1: // Zen
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case 0x8: // Zen+
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case 0x11: // Zen APU
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case 0x18: // Zen+ APU
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data->amps_visible = true;
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val = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; // package type
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if (val == CPUID_PKGTYPE_SP3 || val == CPUID_PKGTYPE_SP3r2) {
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sp3_chip = true;
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// Threadripper / EPYC
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if (data->node_id == 0) {
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data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE0;
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}
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if (data->node_id == 1) {
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data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
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}
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}
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else{
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// Ryzen
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data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
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data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
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}
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ccd_check = 4;
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break;
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case 0x11: // Zen APU
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case 0x18: // Zen+ APU
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data->amps_visible = true;
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data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
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data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
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break;
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case 0x31: // Zen2 Threadripper/EPYC
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sp3_chip = true; // fall through
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data->zen2 = true;
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data->amps_visible = true;
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data->svi_core_addr = F17H_M30H_SVI_TEL_PLANE0;
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data->svi_soc_addr = F17H_M30H_SVI_TEL_PLANE1;
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ccd_check = 8;
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break;
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case 0x71: // Zen2 Ryzen
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data->amps_visible = true;
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data->zen2 = true;
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swapped_addr = true;
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data->amps_visible = true;
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data->svi_core_addr = F17H_M70H_SVI_TEL_PLANE0;
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data->svi_soc_addr = F17H_M70H_SVI_TEL_PLANE1;
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ccd_check = 8;
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break;
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default:
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data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
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data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
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break;
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}
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}
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@ -515,39 +545,6 @@ static int zenpower_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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}
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}
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#ifdef SWAP_CORE_SOC
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swapped_addr = !swapped_addr;
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#endif
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// SVI2 values seems to be only in node #0 or #1
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if (data->node_id == 0 || data->node_id == 1){
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if (swapped_addr) {
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primary_plane = F17H_M01H_SVI_TEL_PLANE1;
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secondary_plane = F17H_M01H_SVI_TEL_PLANE0;
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}
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else {
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primary_plane = F17H_M01H_SVI_TEL_PLANE0;
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secondary_plane = F17H_M01H_SVI_TEL_PLANE1;
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}
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data->read_amdsmn_addr(pdev, data->node_id, primary_plane, &val);
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if (val != 0) {
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if (sp3_chip){
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if (data->node_id == 0) {
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data->svi_soc_addr = primary_plane;
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}
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if (data->node_id == 1) {
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data->svi_core_addr = primary_plane;
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}
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}
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else if (data->node_id == 0) {
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data->svi_core_addr = primary_plane;
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data->svi_soc_addr = secondary_plane;
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}
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}
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}
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for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
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const struct tctl_offset *entry = &tctl_offset_table[i];
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