657 lines
16 KiB
C
657 lines
16 KiB
C
/*
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* Zenpower - Driver for reading temperature, voltage, current and power for AMD 17h CPUs
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*
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* Copyright (c) 2018-2020 Ondrej Čerman
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*
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* This driver is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this driver; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* based on k10temp by Clemens Ladisch
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*
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* Docs:
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* - https://www.kernel.org/doc/Documentation/hwmon/hwmon-kernel-api.txt
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* - https://developer.amd.com/wp-content/resources/56255_3_03.PDF
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*
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* Sources:
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* - Temp monitoring is from k10temp
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* - SVI address and voltage formula is from LibreHardwareMonitor
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* - Current formulas and CCD temp addresses were discovered experimentally
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*/
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#include <linux/hwmon.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/amd_nb.h>
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MODULE_DESCRIPTION("AMD ZEN family CPU Sensors Driver");
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MODULE_AUTHOR("Ondrej Čerman");
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MODULE_LICENSE("GPL");
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MODULE_VERSION("0.1.11");
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#ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_M30H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
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#endif
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#ifndef PCI_DEVICE_ID_AMD_17H_M70H_DF_F3
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#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
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#endif
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#define F17H_M01H_REPORTED_TEMP_CTRL 0x00059800
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#define F17H_M01H_SVI 0x0005A000
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#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xC)
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#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
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#define F17H_M30H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0x14)
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#define F17H_M30H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
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#define F17H_M70H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0x10)
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#define F17H_M70H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0xC)
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#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
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#define F17H_TEMP_ADJUST_MASK 0x80000
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#ifndef HWMON_CHANNEL_INFO
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#define HWMON_CHANNEL_INFO(stype, ...) \
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(&(struct hwmon_channel_info) { \
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.type = hwmon_##stype, \
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.config = (u32 []) { \
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__VA_ARGS__, 0 \
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} \
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})
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#endif
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struct zenpower_data {
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struct pci_dev *pdev;
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void (*read_amdsmn_addr)(struct pci_dev *pdev, u16 node_id, u32 address, u32 *regval);
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u32 svi_core_addr;
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u32 svi_soc_addr;
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u16 node_id;
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u8 cpu_id;
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u8 nodes_per_cpu;
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int temp_offset;
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bool zen2;
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bool kernel_smn_support;
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bool amps_visible;
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bool ccd_visible[8];
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};
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struct tctl_offset {
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u8 model;
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char const *id;
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int offset;
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};
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static const struct tctl_offset tctl_offset_table[] = {
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{ 0x17, "AMD Ryzen 5 1600X", 20000 },
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{ 0x17, "AMD Ryzen 7 1700X", 20000 },
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{ 0x17, "AMD Ryzen 7 1800X", 20000 },
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{ 0x17, "AMD Ryzen 7 2700X", 10000 },
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{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
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{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
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};
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static DEFINE_MUTEX(nb_smu_ind_mutex);
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static bool multicpu = false;
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static umode_t zenpower_is_visible(const void *rdata,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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const struct zenpower_data *data = rdata;
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switch (type) {
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case hwmon_temp:
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if (channel >= 2 && data->ccd_visible[channel-2] == false) // Tccd1-8
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return 0;
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break;
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case hwmon_curr:
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case hwmon_power:
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if (data->amps_visible == false)
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return 0;
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if (channel == 0 && data->svi_core_addr == 0)
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return 0;
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if (channel == 1 && data->svi_soc_addr == 0)
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return 0;
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break;
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case hwmon_in:
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if (channel == 0) // fake item to align different indexing,
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return 0; // see note at zenpower_info
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if (channel == 1 && data->svi_core_addr == 0)
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return 0;
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if (channel == 2 && data->svi_soc_addr == 0)
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return 0;
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break;
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default:
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break;
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}
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return 0444;
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}
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static u32 plane_to_vcc(u32 p)
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{
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u32 vdd_cor;
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vdd_cor = (p >> 16) & 0xff;
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// U = 1550 - 6.25 * vddcor
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return 1550 - ((625 * vdd_cor) / 100);
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}
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static u32 get_core_current(u32 plane, bool zen2)
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{
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u32 idd_cor, fc;
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idd_cor = plane & 0xff;
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// I = 1039.211 * iddcor
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// I = 658.823 * iddcor
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fc = zen2 ? 658823 : 1039211;
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return (fc * idd_cor) / 1000;
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}
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static u32 get_soc_current(u32 plane, bool zen2)
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{
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u32 idd_cor, fc;
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idd_cor = plane & 0xff;
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// I = 360.772 * iddcor
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// I = 294.3 * iddcor
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fc = zen2 ? 294300 : 360772;
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return (fc * idd_cor) / 1000;
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}
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static unsigned int get_ctl_temp(struct zenpower_data *data)
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{
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unsigned int temp;
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u32 regval;
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data->read_amdsmn_addr(data->pdev, data->node_id,
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F17H_M01H_REPORTED_TEMP_CTRL, ®val);
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temp = (regval >> 21) * 125;
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if (regval & F17H_TEMP_ADJUST_MASK)
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temp -= 49000;
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return temp;
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}
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static unsigned int get_ccd_temp(struct zenpower_data *data, u32 ccd_addr)
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{
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u32 regval;
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data->read_amdsmn_addr(data->pdev, data->node_id, ccd_addr, ®val);
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return (regval & 0xfff) * 125 - 305000;
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}
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int static debug_addrs_arr[] = {
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F17H_M01H_SVI + 0x8, F17H_M01H_SVI + 0xC, F17H_M01H_SVI + 0x10,
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F17H_M01H_SVI + 0x14, 0x000598BC, 0x0005994C, F17H_M70H_CCD_TEMP(0),
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F17H_M70H_CCD_TEMP(1), F17H_M70H_CCD_TEMP(2), F17H_M70H_CCD_TEMP(3),
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F17H_M70H_CCD_TEMP(4), F17H_M70H_CCD_TEMP(5), F17H_M70H_CCD_TEMP(6),
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F17H_M70H_CCD_TEMP(7)
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};
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static ssize_t debug_data_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int i, len = 0;
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struct zenpower_data *data = dev_get_drvdata(dev);
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u32 smndata;
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len += sprintf(buf + len, "KERN_SUP: %d\n", data->kernel_smn_support);
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len += sprintf(buf + len, "NODE%d; CPU%d; ", data->node_id, data->cpu_id);
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len += sprintf(buf + len, "N/CPU: %d\n", data->nodes_per_cpu);
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for (i = 0; i < ARRAY_SIZE(debug_addrs_arr); i++){
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data->read_amdsmn_addr(data->pdev, data->node_id, debug_addrs_arr[i], &smndata);
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len += sprintf(buf + len, "%08x = %08x\n", debug_addrs_arr[i], smndata);
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}
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return len;
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}
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static int zenpower_read(struct device *dev, enum hwmon_sensor_types type,
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u32 attr, int channel, long *val)
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{
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struct zenpower_data *data = dev_get_drvdata(dev);
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u32 plane;
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switch (type) {
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// Temperatures
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case hwmon_temp:
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switch (attr) {
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case hwmon_temp_input:
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switch (channel) {
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case 0: // Tdie
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*val = get_ctl_temp(data) - data->temp_offset;
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break;
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case 1: // Tctl
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*val = get_ctl_temp(data);
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break;
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case 2 ... 9: // Tccd1-8
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*val = get_ccd_temp(data, F17H_M70H_CCD_TEMP(channel-2));
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break;
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default:
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return -EOPNOTSUPP;
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}
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break;
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case hwmon_temp_max: // Tdie max
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// source: https://www.amd.com/en/products/cpu/amd-ryzen-7-3700x
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// other cpus have also same* Tmax on AMD website
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// * = when taking into consideration a tctl offset
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*val = 95 * 1000;
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break;
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default:
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return -EOPNOTSUPP;
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}
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break;
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// Voltage
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case hwmon_in:
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if (channel == 0)
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return -EOPNOTSUPP;
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channel -= 1; // hwmon_in have different indexing, see note at zenpower_info
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// fall through
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// Power / Current
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case hwmon_curr:
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case hwmon_power:
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if (attr != hwmon_in_input && attr != hwmon_curr_input &&
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attr != hwmon_power_input) {
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return -EOPNOTSUPP;
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}
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switch (channel) {
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case 0: // Core SVI2
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data->read_amdsmn_addr(data->pdev, data->node_id,
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data->svi_core_addr, &plane);
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break;
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case 1: // SoC SVI2
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data->read_amdsmn_addr(data->pdev, data->node_id,
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data->svi_soc_addr, &plane);
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break;
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default:
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return -EOPNOTSUPP;
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}
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switch (type) {
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case hwmon_in:
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*val = plane_to_vcc(plane);
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break;
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case hwmon_curr:
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*val = (channel == 0) ?
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get_core_current(plane, data->zen2):
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get_soc_current(plane, data->zen2);
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break;
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case hwmon_power:
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*val = (channel == 0) ?
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get_core_current(plane, data->zen2) * plane_to_vcc(plane):
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get_soc_current(plane, data->zen2) * plane_to_vcc(plane);
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break;
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default:
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break;
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}
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static const char *zenpower_temp_label[][10] = {
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{
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"Tdie",
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"Tctl",
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"Tccd1",
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"Tccd2",
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"Tccd3",
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"Tccd4",
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"Tccd5",
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"Tccd6",
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"Tccd7",
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"Tccd8",
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},
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{
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"cpu0 Tdie",
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"cpu0 Tctl",
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"cpu0 Tccd1",
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"cpu0 Tccd2",
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"cpu0 Tccd3",
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"cpu0 Tccd4",
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"cpu0 Tccd5",
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"cpu0 Tccd6",
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"cpu0 Tccd7",
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"cpu0 Tccd8",
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},
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{
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"cpu1 Tdie",
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"cpu1 Tctl",
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"cpu1 Tccd1",
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"cpu1 Tccd2",
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"cpu1 Tccd3",
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"cpu1 Tccd4",
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"cpu1 Tccd5",
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"cpu1 Tccd6",
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"cpu1 Tccd7",
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"cpu1 Tccd8",
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}
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};
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static const char *zenpower_in_label[][3] = {
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{
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"",
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"SVI2_Core",
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"SVI2_SoC",
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},
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{
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"",
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"cpu0 SVI2_Core",
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"cpu0 SVI2_SoC",
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},
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{
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"",
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"cpu1 SVI2_Core",
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"cpu1 SVI2_SoC",
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}
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};
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static const char *zenpower_curr_label[][2] = {
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{
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"SVI2_C_Core",
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"SVI2_C_SoC",
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},
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{
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"cpu0 SVI2_C_Core",
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"cpu0 SVI2_C_SoC",
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},
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{
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"cpu1 SVI2_C_Core",
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"cpu1 SVI2_C_SoC",
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}
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};
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static const char *zenpower_power_label[][2] = {
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{
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"SVI2_P_Core",
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"SVI2_P_SoC",
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},
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{
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"cpu0 SVI2_P_Core",
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"cpu0 SVI2_P_SoC",
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},
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{
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"cpu1 SVI2_P_Core",
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"cpu1 SVI2_P_SoC",
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}
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};
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static int zenpower_read_labels(struct device *dev,
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enum hwmon_sensor_types type, u32 attr,
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int channel, const char **str)
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{
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struct zenpower_data *data;
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u8 i = 0;
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if (multicpu) {
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data = dev_get_drvdata(dev);
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if (data->cpu_id <= 1)
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i = data->cpu_id + 1;
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}
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switch (type) {
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case hwmon_temp:
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*str = zenpower_temp_label[i][channel];
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break;
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case hwmon_in:
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*str = zenpower_in_label[i][channel];
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break;
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case hwmon_curr:
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*str = zenpower_curr_label[i][channel];
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break;
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case hwmon_power:
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*str = zenpower_power_label[i][channel];
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static void kernel_smn_read(struct pci_dev *pdev, u16 node_id, u32 address, u32 *regval)
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{
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amd_smn_read(node_id, address, regval);
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}
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// fallback method from k10temp
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// may return inaccurate results on multi-die chips
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static void nb_index_read(struct pci_dev *pdev, u16 node_id, u32 address, u32 *regval)
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{
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mutex_lock(&nb_smu_ind_mutex);
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pci_bus_write_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0x60, address);
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pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0x64, regval);
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mutex_unlock(&nb_smu_ind_mutex);
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}
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static const struct hwmon_channel_info *zenpower_info[] = {
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HWMON_CHANNEL_INFO(temp,
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HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_LABEL, // Tdie
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HWMON_T_INPUT | HWMON_T_LABEL, // Tctl
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd1
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd2
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd3
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd4
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd5
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd6
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HWMON_T_INPUT | HWMON_T_LABEL, // Tccd7
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HWMON_T_INPUT | HWMON_T_LABEL), // Tccd8
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HWMON_CHANNEL_INFO(in,
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HWMON_I_LABEL, // everything is using 1 based indexing except
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// hwmon_in - that is using 0 based indexing
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// let's make fake item so corresponding SVI2 data is
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// associated with same index
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HWMON_I_INPUT | HWMON_I_LABEL, // Core Voltage (SVI2)
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HWMON_I_INPUT | HWMON_I_LABEL), // SoC Voltage (SVI2)
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HWMON_CHANNEL_INFO(curr,
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HWMON_C_INPUT | HWMON_C_LABEL, // Core Current (SVI2)
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HWMON_C_INPUT | HWMON_C_LABEL), // SoC Current (SVI2)
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HWMON_CHANNEL_INFO(power,
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HWMON_P_INPUT | HWMON_P_LABEL, // Core Power (SVI2)
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HWMON_P_INPUT | HWMON_P_LABEL), // SoC Power (SVI2)
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NULL
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};
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static const struct hwmon_ops zenpower_hwmon_ops = {
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.is_visible = zenpower_is_visible,
|
|
.read = zenpower_read,
|
|
.read_string = zenpower_read_labels,
|
|
};
|
|
|
|
static const struct hwmon_chip_info zenpower_chip_info = {
|
|
.ops = &zenpower_hwmon_ops,
|
|
.info = zenpower_info,
|
|
};
|
|
|
|
static DEVICE_ATTR_RO(debug_data);
|
|
|
|
static struct attribute *zenpower_attrs[] = {
|
|
&dev_attr_debug_data.attr,
|
|
NULL
|
|
};
|
|
|
|
static const struct attribute_group zenpower_group = {
|
|
.attrs = zenpower_attrs
|
|
};
|
|
__ATTRIBUTE_GROUPS(zenpower);
|
|
|
|
static int zenpower_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct zenpower_data *data;
|
|
struct device *hwmon_dev;
|
|
struct pci_dev *misc;
|
|
int i, ccd_check = 0;
|
|
bool multinode;
|
|
u8 node_of_cpu;
|
|
u32 val;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
data->zen2 = false;
|
|
data->pdev = pdev;
|
|
data->temp_offset = 0;
|
|
data->read_amdsmn_addr = nb_index_read;
|
|
data->kernel_smn_support = false;
|
|
data->svi_core_addr = false;
|
|
data->svi_soc_addr = false;
|
|
data->amps_visible = false;
|
|
data->node_id = 0;
|
|
for (i = 0; i < 8; i++) {
|
|
data->ccd_visible[i] = false;
|
|
}
|
|
|
|
for (i = 0; i < amd_nb_num(); i++) {
|
|
misc = node_to_amd_nb(i)->misc;
|
|
if (pdev->vendor == misc->vendor && pdev->device == misc->device) {
|
|
data->kernel_smn_support = true;
|
|
data->read_amdsmn_addr = kernel_smn_read;
|
|
data->node_id = amd_pci_dev_to_node_id(pdev);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// CPUID_Fn8000001E_ECX [Node Identifiers] (Core::X86::Cpuid::NodeId)
|
|
// 10:8 NodesPerProcessor
|
|
data->nodes_per_cpu = 1 + ((cpuid_ecx(0x8000001E) >> 8) & 0b111);
|
|
multinode = (data->nodes_per_cpu > 1);
|
|
|
|
node_of_cpu = data->node_id % data->nodes_per_cpu;
|
|
data->cpu_id = data->node_id / data->nodes_per_cpu;
|
|
|
|
if (data->cpu_id > 0)
|
|
multicpu = true;
|
|
|
|
if (boot_cpu_data.x86 == 0x17) {
|
|
switch (boot_cpu_data.x86_model) {
|
|
case 0x1: // Zen
|
|
case 0x8: // Zen+
|
|
data->amps_visible = true;
|
|
|
|
if (multinode) { // Threadripper / EPYC
|
|
if (node_of_cpu == 0) {
|
|
data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE0;
|
|
}
|
|
if (node_of_cpu == 1) {
|
|
data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
|
|
}
|
|
}
|
|
else { // Ryzen
|
|
data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
|
|
data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
|
|
}
|
|
ccd_check = 4;
|
|
break;
|
|
|
|
case 0x11: // Zen APU
|
|
case 0x18: // Zen+ APU
|
|
data->amps_visible = true;
|
|
data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
|
|
data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
|
|
break;
|
|
|
|
case 0x31: // Zen2 Threadripper/EPYC
|
|
data->zen2 = true;
|
|
data->amps_visible = true;
|
|
data->svi_core_addr = F17H_M30H_SVI_TEL_PLANE0;
|
|
data->svi_soc_addr = F17H_M30H_SVI_TEL_PLANE1;
|
|
ccd_check = 8;
|
|
break;
|
|
|
|
case 0x71: // Zen2 Ryzen
|
|
data->zen2 = true;
|
|
data->amps_visible = true;
|
|
data->svi_core_addr = F17H_M70H_SVI_TEL_PLANE0;
|
|
data->svi_soc_addr = F17H_M70H_SVI_TEL_PLANE1;
|
|
ccd_check = 8;
|
|
break;
|
|
|
|
default:
|
|
data->svi_core_addr = F17H_M01H_SVI_TEL_PLANE0;
|
|
data->svi_soc_addr = F17H_M01H_SVI_TEL_PLANE1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < ccd_check; i++) {
|
|
data->read_amdsmn_addr(pdev, data->node_id,
|
|
F17H_M70H_CCD_TEMP(i), &val);
|
|
if ((val & 0xfff) > 0) {
|
|
data->ccd_visible[i] = true;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
|
|
const struct tctl_offset *entry = &tctl_offset_table[i];
|
|
|
|
if (boot_cpu_data.x86 == entry->model &&
|
|
strstr(boot_cpu_data.x86_model_id, entry->id)) {
|
|
data->temp_offset = entry->offset;
|
|
break;
|
|
}
|
|
}
|
|
|
|
hwmon_dev = devm_hwmon_device_register_with_info(
|
|
dev, "zenpower", data, &zenpower_chip_info, zenpower_groups
|
|
);
|
|
|
|
return PTR_ERR_OR_ZERO(hwmon_dev);
|
|
}
|
|
|
|
static const struct pci_device_id zenpower_id_table[] = {
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
|
|
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, zenpower_id_table);
|
|
|
|
static struct pci_driver zenpower_driver = {
|
|
.name = "zenpower",
|
|
.id_table = zenpower_id_table,
|
|
.probe = zenpower_probe,
|
|
};
|
|
|
|
module_pci_driver(zenpower_driver);
|